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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 254

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Rev Log message Author Age Path
254 Fixed a latch in the design creep 5583d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
253 Changed the rw_mem signal name in the hierarchy creep 5606d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
246 Added some older files plus the first syn script creep 5613d 19h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
243 Fixing STA_IDY bug creep 5655d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
242 Bug regardind the STA_IDY opcode creep 5655d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
212 Bug #56: ZPX page crossing. creep 5681d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5684d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
202 Bug #49: RTI and RTS behavior was recoded. creep 5687d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
200 Bug #48: SP wrong after decrement. creep 5687d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
199 Fixed two warning messages at the FSM. creep 5687d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
196 Syncing both repositories. creep 5688d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
195 FSM was locking on TSX/TXS. creep 5688d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
194 Fixing bug #45 creep 5688d 19h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
146 Fixed ticket #13: reset behavior in the FSM. creep 5710d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5715d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
120 Added some extra commentaries. creep 5717d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
117 Fixed the top level and connected the entire project. creep 5717d 19h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
115 Renamed the signal control. It is mem_rw now. creep 5717d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
112 Created a global timescale file for the project. creep 5717d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
111 Performed some linting after coding was finished. creep 5718d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

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