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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Rev 92

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92 Absolute indexed mode working properly. All cases were simulated. creep 5709d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
91 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. creep 5709d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
89 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated. creep 5709d 09h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5709d 09h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5710d 01h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
86 Zero page indexed mode is working fine. creep 5710d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
78 ZPG coded and simulated. creep 5711d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
76 ABS write instructions were not simulated.
Also added some initial ZPG simulation.		 creep 5711d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5711d 05h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5715d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
67 File name change to lowercase. HAL says so! creep 5715d 06h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v

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