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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm_tb.v] - Rev 95

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95 IDX addressing mode is also 100%, coded and simulated. creep 5577d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5577d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
92 Absolute indexed mode working properly. All cases were simulated. creep 5578d 03h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
91 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page IS crossed is coded and simulated. creep 5578d 03h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
89 Absolute indexed mode, READ_MODIFY_WRITE TYPE instruction when page is NOT crossed is coded and simulated. creep 5578d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5578d 05h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5578d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
86 Zero page indexed mode is working fine. creep 5579d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
78 ZPG coded and simulated. creep 5579d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
76 ABS write instructions were not simulated.
Also added some initial ZPG simulation.		 creep 5579d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5580d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5583d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v
67 File name change to lowercase. HAL says so! creep 5584d 01h /t6507lp/trunk/rtl/verilog/t6507lp_fsm_tb.v

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