URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp] - Rev 264

Rev	Log message	Author	Age	Path
264	Final synthesis results. Gates, sdc, tcl, conf, etc.	creep	5403d 09h	/t6507lp
263	Added the final reports from synthesis without a VCD	creep	5403d 09h	/t6507lp
262	Final synthesis script.	creep	5403d 09h	/t6507lp
261	Added a better clock gating scheme with enable sharing	creep	5403d 12h	/t6507lp
260	removing useless files	creep	5406d 06h	/t6507lp
259	sync	creep	5406d 06h	/t6507lp
258	Fixed the input parametric testing logic, removed a pad.	creep	5406d 06h	/t6507lp
257	Modified script for DFT	creep	5428d 09h	/t6507lp
256	fp files	creep	5428d 09h	/t6507lp
255	Changed the PADS verilog description to minimize violations	creep	5428d 09h	/t6507lp
254	Fixed a latch in the design	creep	5428d 09h	/t6507lp
253	Changed the rw_mem signal name in the hierarchy	creep	5451d 10h	/t6507lp
252	Added a stubs file for the pads.	creep	5451d 10h	/t6507lp
251	Added the io wrapper	creep	5451d 13h	/t6507lp
250	Synthesis script changed	creep	5451d 13h	/t6507lp
249	Renamed the synthesis script	creep	5452d 09h	/t6507lp
248	Added a low power synthesis script	creep	5457d 08h	/t6507lp
247	Added the cpu mapped verilog	creep	5457d 08h	/t6507lp
246	Added some older files plus the first syn script	creep	5458d 13h	/t6507lp
245	Added a few dirs for the synthesis	creep	5458d 13h	/t6507lp