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[/] [test_project/] [trunk/] [bench/] [sysc/] [src/] [OrpsocMain.cpp] - Rev 55

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Rev Log message Author Age Path
55 Systemc vcd file name based on test name which is passed via command line when the executable is run julius 5651d 20h /test_project/trunk/bench/sysc/src/OrpsocMain.cpp
52 Enabled own printf function using UART as output julius 5652d 12h /test_project/trunk/bench/sysc/src/OrpsocMain.cpp
51 Added SystemC Uart model julius 5655d 01h /test_project/trunk/bench/sysc/src/OrpsocMain.cpp
50 Tracing enabled on Verilator model julius 5655d 15h /test_project/trunk/bench/sysc/src/OrpsocMain.cpp
48 Closer to working verilator build julius 5656d 16h /test_project/trunk/bench/sysc/src/OrpsocMain.cpp
47 Basic verilator model getting closer. Included more modules from the example by Jeremy Bennett. Final cplusplus executable from verilator output fails to link properly julius 5656d 20h /test_project/trunk/bench/sysc/src/OrpsocMain.cpp
44 Beginnings of verilator build - much still to do but the design can now at least be verilated julius 5664d 20h /test_project/trunk/bench/sysc/src/OrpsocMain.cpp

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