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[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench.v] - Rev 54

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54 Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at julius 5668d 20h /test_project/trunk/bench/verilog/orpsoc_testbench.v
46 Flash memory now also disabled when SDRAM disabled, which is by default. Ethernet now enabled by defining USE_ETHERNET, otherwise it is disabled by default. Default icarus tests now very fast due to this julius 5674d 22h /test_project/trunk/bench/verilog/orpsoc_testbench.v
45 Many updates including internal SRAM instead of SDRAM as default, so inclusion of the SRAM model, a new VMEM generation program, and script and testbench updates to allow the switching on and off for SDRAM, which as mentioned is now off by default julius 5675d 14h /test_project/trunk/bench/verilog/orpsoc_testbench.v
43 Added some verilator lint controls, made icarus script much more concise. First stage of verilation now works julius 5681d 22h /test_project/trunk/bench/verilog/orpsoc_testbench.v
40 Change name of file and module of orpsoc_top module julius 5682d 17h /test_project/trunk/bench/verilog/orpsoc_testbench.v
34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5683d 20h /test_project/trunk/bench/verilog/orpsoc_testbench.v
32 Looks like basic icarus tests passing. Todo is a list of timeouts for the rtl sim julius 5685d 12h /test_project/trunk/bench/verilog/orpsoc_testbench.v
31 Further progress with orpsoc test setup julius 5685d 13h /test_project/trunk/bench/verilog/orpsoc_testbench.v
30 Updating bench julius 5687d 18h /test_project/trunk/bench/verilog/orpsoc_testbench.v
26 Adding testbench and makefile update julius 5688d 22h /test_project/trunk/bench/verilog/orpsoc_testbench.v

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