OpenCores
URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [bench/] [verilog/] [orpsoc_testbench_defines.v] - Rev 54

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
54 Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at julius 5652d 01h /test_project/trunk/bench/verilog/orpsoc_testbench_defines.v
52 Enabled own printf function using UART as output julius 5652d 15h /test_project/trunk/bench/verilog/orpsoc_testbench_defines.v
34 Fixed up couple of things. Changed way the test name is defined in sim Makefile julius 5667d 01h /test_project/trunk/bench/verilog/orpsoc_testbench_defines.v
30 Updating bench julius 5670d 23h /test_project/trunk/bench/verilog/orpsoc_testbench_defines.v
26 Adding testbench and makefile update julius 5672d 03h /test_project/trunk/bench/verilog/orpsoc_testbench_defines.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.