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[/] [tinycpu/] [trunk/] [docs/] [design.md.txt] - Rev 29

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29 Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad.		 earlz 4389d 11h /tinycpu/trunk/docs/design.md.txt
27 Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later		 earlz 4390d 12h /tinycpu/trunk/docs/design.md.txt
25 Wait for memory state now works as expected, and opcode `mov [reg], immd` works now earlz 4390d 17h /tinycpu/trunk/docs/design.md.txt
21 The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. earlz 4392d 03h /tinycpu/trunk/docs/design.md.txt
19 Got beginning of core/decoder for the CPU earlz 4393d 04h /tinycpu/trunk/docs/design.md.txt
17 Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct		 earlz 4397d 04h /tinycpu/trunk/docs/design.md.txt
16 Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.		 earlz 4400d 06h /tinycpu/trunk/docs/design.md.txt
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4402d 11h /tinycpu/trunk/docs/design.md.txt
5 Modified registerfile to be dual-port for both read and write earlz 4408d 05h /tinycpu/trunk/docs/design.md.txt
4 Added internal memory interface
Updated design		 earlz 4408d 13h /tinycpu/trunk/docs/design.md.txt
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming		 earlz 4409d 05h /tinycpu/trunk/docs/design.md.txt

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