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[/] [tinycpu/] [trunk/] [src/] [core.vhd] - Rev 29

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29 Well, added a testcase for testing the ALU bitwise operations and found a very large problem.
I'm pretty sure that the decoder needs to be partially unclocked because it essentially makes the ALU clocked how it is now, which is very bad.		 earlz 4399d 18h /tinycpu/trunk/src/core.vhd
28 Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
Now it's truly single-cycle and without all the weird regIn stuff on the carryovers		 earlz 4400d 12h /tinycpu/trunk/src/core.vhd
27 Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile.
As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later		 earlz 4400d 18h /tinycpu/trunk/src/core.vhd
25 Wait for memory state now works as expected, and opcode `mov [reg], immd` works now earlz 4400d 23h /tinycpu/trunk/src/core.vhd
24 Good news, mov to IP actually works as expected! earlz 4401d 17h /tinycpu/trunk/src/core.vhd
23 Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core		 earlz 4401d 17h /tinycpu/trunk/src/core.vhd
21 The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. earlz 4402d 09h /tinycpu/trunk/src/core.vhd
20 fuck it. All sorts of broken, will try to fix it tomorrow earlz 4403d 09h /tinycpu/trunk/src/core.vhd
19 Got beginning of core/decoder for the CPU earlz 4403d 10h /tinycpu/trunk/src/core.vhd

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