URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [testbench/] [core_tb.vhd] - Rev 28

Rev	Log message	Author	Age	Path
28	Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted. Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle. Now it's truly single-cycle and without all the weird regIn stuff on the carryovers	earlz	4389d 11h	/tinycpu/trunk/testbench/core_tb.vhd
27	Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile. As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later	earlz	4389d 17h	/tinycpu/trunk/testbench/core_tb.vhd
26	Added extra check to make sure fetcher works properly after memory write	earlz	4389d 18h	/tinycpu/trunk/testbench/core_tb.vhd
25	Wait for memory state now works as expected, and opcode `mov [reg], immd` works now	earlz	4389d 22h	/tinycpu/trunk/testbench/core_tb.vhd
24	Good news, mov to IP actually works as expected!	earlz	4390d 16h	/tinycpu/trunk/testbench/core_tb.vhd
21	The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it.	earlz	4391d 08h	/tinycpu/trunk/testbench/core_tb.vhd
20	fuck it. All sorts of broken, will try to fix it tomorrow	earlz	4392d 08h	/tinycpu/trunk/testbench/core_tb.vhd
19	Got beginning of core/decoder for the CPU	earlz	4392d 10h	/tinycpu/trunk/testbench/core_tb.vhd