URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [testbench/] [memory_tb.vhd] - Rev 41

Rev	Log message	Author	Age	Path
41	Well, finally got ports to work properly without latches. Had to reimplement a specific more complex form of RAM basically. The code is horrid, but testcases pass	earlz	4547d 07h	/tinycpu/trunk/testbench/memory_tb.vhd
37	Worked on the assembler more Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some	earlz	4552d 07h	/tinycpu/trunk/testbench/memory_tb.vhd
18	Finished memory controller	earlz	4564d 18h	/tinycpu/trunk/testbench/memory_tb.vhd
7	Changed memory to fix bound check error Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)	earlz	4575d 17h	/tinycpu/trunk/testbench/memory_tb.vhd
4	Added internal memory interface Updated design	earlz	4576d 16h	/tinycpu/trunk/testbench/memory_tb.vhd