URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [testbench/] [top_tb.vhd] - Rev 39

Rev	Log message	Author	Age	Path
39	A lot of work in the assembler. It now supports nearly every opcode implemented and is a lot cleaner Added a bootrom. There isn't really a point in testbenching this.. I'm not for sure how I would, and it will change so much in these early days that it'll be pointless I think Everything should be ready to go for a test on actual hardware now!	earlz	4393d 09h	/tinycpu/trunk/testbench/top_tb.vhd
37	Worked on the assembler more Added a memory mapped port to memory.vhd. This change causes a lot of latches to be inferred in synthesis however, so this will have to change some	earlz	4395d 10h	/tinycpu/trunk/testbench/top_tb.vhd
28	Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted. Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle. Now it's truly single-cycle and without all the weird regIn stuff on the carryovers	earlz	4401d 12h	/tinycpu/trunk/testbench/top_tb.vhd
25	Wait for memory state now works as expected, and opcode `mov [reg], immd` works now	earlz	4401d 23h	/tinycpu/trunk/testbench/top_tb.vhd
23	Added top module for testing how our memory and cpu will work together. (hint: success) Messing around with a small timing issue in core	earlz	4402d 17h	/tinycpu/trunk/testbench/top_tb.vhd