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[/] [tinycpu/] [trunk] - Rev 16

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16 Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.
earlz 4436d 06h /tinycpu/trunk
15 Added README, LICENSE, and the (so far not created) incdec component earlz 4438d 03h /tinycpu/trunk
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4438d 11h /tinycpu/trunk
13 Forgot about the new library I added earlz 4438d 14h /tinycpu/trunk
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD
earlz 4438d 15h /tinycpu/trunk
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4442d 04h /tinycpu/trunk
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4442d 05h /tinycpu/trunk
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4442d 12h /tinycpu/trunk
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing
earlz 4443d 12h /tinycpu/trunk
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)
earlz 4443d 13h /tinycpu/trunk
6 Reworked memory code to hopefully synthesize better earlz 4443d 17h /tinycpu/trunk
5 Modified registerfile to be dual-port for both read and write earlz 4444d 04h /tinycpu/trunk
4 Added internal memory interface
Updated design
earlz 4444d 12h /tinycpu/trunk
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming
earlz 4445d 04h /tinycpu/trunk
2 Initial commit earlz 4445d 06h /tinycpu/trunk
1 The project and the structure was created root 4445d 08h /tinycpu/trunk

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