OpenCores
URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk] - Rev 19

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
19 Got beginning of core/decoder for the CPU earlz 4464d 05h /tinycpu/trunk
18 Finished memory controller earlz 4467d 15h /tinycpu/trunk
17 Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct		 earlz 4468d 05h /tinycpu/trunk
16 Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.		 earlz 4471d 07h /tinycpu/trunk
15 Added README, LICENSE, and the (so far not created) incdec component earlz 4473d 04h /tinycpu/trunk
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4473d 13h /tinycpu/trunk
13 Forgot about the new library I added earlz 4473d 15h /tinycpu/trunk
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD		 earlz 4473d 16h /tinycpu/trunk
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4477d 05h /tinycpu/trunk
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4477d 06h /tinycpu/trunk
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4477d 13h /tinycpu/trunk
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing		 earlz 4478d 13h /tinycpu/trunk
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)		 earlz 4478d 14h /tinycpu/trunk
6 Reworked memory code to hopefully synthesize better earlz 4478d 18h /tinycpu/trunk
5 Modified registerfile to be dual-port for both read and write earlz 4479d 06h /tinycpu/trunk
4 Added internal memory interface
Updated design		 earlz 4479d 14h /tinycpu/trunk
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming		 earlz 4480d 06h /tinycpu/trunk
2 Initial commit earlz 4480d 07h /tinycpu/trunk
1 The project and the structure was created root 4480d 09h /tinycpu/trunk

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.