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[/] [tinycpu] - Rev 15

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15 Added README, LICENSE, and the (so far not created) incdec component earlz 4572d 03h /tinycpu
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4572d 11h /tinycpu
13 Forgot about the new library I added earlz 4572d 14h /tinycpu
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD		 earlz 4572d 15h /tinycpu
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4576d 04h /tinycpu
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4576d 05h /tinycpu
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4576d 12h /tinycpu
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing		 earlz 4577d 12h /tinycpu
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)		 earlz 4577d 13h /tinycpu
6 Reworked memory code to hopefully synthesize better earlz 4577d 17h /tinycpu
5 Modified registerfile to be dual-port for both read and write earlz 4578d 05h /tinycpu
4 Added internal memory interface
Updated design		 earlz 4578d 13h /tinycpu
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming		 earlz 4579d 05h /tinycpu
2 Initial commit earlz 4579d 06h /tinycpu
1 The project and the structure was created root 4579d 08h /tinycpu

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