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[/] [tinycpu] - Rev 20

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20 fuck it. All sorts of broken, will try to fix it tomorrow earlz 4529d 09h /tinycpu
19 Got beginning of core/decoder for the CPU earlz 4529d 11h /tinycpu
18 Finished memory controller earlz 4532d 20h /tinycpu
17 Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct
earlz 4533d 10h /tinycpu
16 Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.
earlz 4536d 12h /tinycpu
15 Added README, LICENSE, and the (so far not created) incdec component earlz 4538d 10h /tinycpu
14 Added ALU with all the operations we'll need. Synthesizes as well trivially earlz 4538d 18h /tinycpu
13 Forgot about the new library I added earlz 4538d 21h /tinycpu
12 registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD
earlz 4538d 21h /tinycpu
11 Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge earlz 4542d 11h /tinycpu
10 Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs earlz 4542d 11h /tinycpu
9 Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench earlz 4542d 19h /tinycpu
8 Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing
earlz 4543d 18h /tinycpu
7 Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000)
earlz 4543d 19h /tinycpu
6 Reworked memory code to hopefully synthesize better earlz 4544d 00h /tinycpu
5 Modified registerfile to be dual-port for both read and write earlz 4544d 11h /tinycpu
4 Added internal memory interface
Updated design
earlz 4544d 19h /tinycpu
3 Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming
earlz 4545d 11h /tinycpu
2 Initial commit earlz 4545d 12h /tinycpu
1 The project and the structure was created root 4545d 15h /tinycpu

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