URL https://opencores.org/ocsvn/ts7300_opencore/ts7300_opencore/trunk

Subversion Repositories ts7300_opencore

[/] [ts7300_opencore/] [trunk/] [altera_ram.v] - Rev 5

Rev	Log message	Author	Age	Path
5	New directory structure.	root	5733d 04h	/ts7300_opencore/trunk/altera_ram.v
2	Initial import of ts7300_opencore. Quartus II project tree for Technologic Systems TS-7300 FPGA Linux Computer. Contains WISHBONE bridge verilog as well as pin locks, timing constraints, and various other Quartus II project metadata. Also included is a sample implementation of the open-ethernet core as well as a stub WISHBONE slave demonstrating a 32-bit register in the address space of the ARM9 CPU running Linux.	joff	6734d 13h	/trunk/altera_ram.v