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[/] [tv80/] [trunk/] [rtl] - Rev 89

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Rev Log message Author Age Path
89 RTL and environment fixes for nmi bug ghutchis 5356d 05h /tv80/trunk/rtl
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5357d 20h /tv80/trunk/rtl
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5373d 03h /tv80/trunk/rtl
84 New directory structure. root 5596d 15h /tv80/trunk/rtl
83 Some fixes from Guy-- replace case with casex. hharte 5669d 21h /trunk/rtl
82 Clean up spacing hharte 5679d 17h /trunk/rtl
81 Initial version of TV80 Wishbone Wrapper hharte 5679d 17h /trunk/rtl
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6779d 06h /trunk/rtl
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6822d 07h /trunk/rtl
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6933d 08h /trunk/rtl
71 Ported UART from T80 ghutchis 7006d 07h /trunk/rtl
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic		 ghutchis 7065d 03h /trunk/rtl
60 Added ifdef TV80_REFRESH, to remove refresh logic by default. Also
ran untabify to remove tabs from source code.		 ghutchis 7100d 06h /trunk/rtl
58 Made TX path async
Made TX clock input instead of output		 ghutchis 7139d 17h /trunk/rtl
52 Added simple GMII-like interface for testing ghutchis 7142d 00h /trunk/rtl
45 Added negedge version of top ghutchis 7157d 03h /trunk/rtl
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7185d 01h /trunk/rtl
24 tv80s.v ghutchis 7213d 17h /trunk/rtl
23 Completed conversion to one-hot encoding ghutchis 7226d 07h /trunk/rtl
22 Changed starting state for one-hot tstate ghutchis 7226d 07h /trunk/rtl

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