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[/] [tv80/] [trunk] - Rev 89

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Rev Log message Author Age Path
89 RTL and environment fixes for nmi bug ghutchis 5374d 07h /tv80/trunk
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5375d 22h /tv80/trunk
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5391d 06h /tv80/trunk
84 New directory structure. root 5614d 17h /tv80/trunk
83 Some fixes from Guy-- replace case with casex. hharte 5688d 00h /trunk
82 Clean up spacing hharte 5697d 20h /trunk
81 Initial version of TV80 Wishbone Wrapper hharte 5697d 20h /trunk
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.		 ghutchis 6797d 08h /trunk
79 Added JR self-checking test ghutchis 6797d 08h /trunk
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6840d 10h /trunk
77 Added back files lost after server crash ghutchis 6872d 04h /trunk
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.		 ghutchis 6951d 10h /trunk
74 Changed default for T2Write to be 1, to match expected behavior for
most users.		 ghutchis 6951d 11h /trunk
73 Added RC4 encrypt/decrypt test ghutchis 6963d 06h /trunk
72 Added copyright header ghutchis 6963d 06h /trunk
71 Ported UART from T80 ghutchis 7024d 10h /trunk
70 Added test for T16450 UART ghutchis 7075d 04h /trunk
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7075d 04h /trunk
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.		 ghutchis 7083d 05h /trunk
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.		 ghutchis 7083d 05h /trunk

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