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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_regs.v] - Rev 58

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58 After reset modem status register MSR should be reset. mohor 8205d 16h /uart16550/trunk/rtl/verilog/uart_regs.v
56 thre irq should be cleared only when being source of interrupt. mohor 8206d 16h /uart16550/trunk/rtl/verilog/uart_regs.v
54 LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). mohor 8207d 17h /uart16550/trunk/rtl/verilog/uart_regs.v
52 Scratch register added gorban 8209d 06h /uart16550/trunk/rtl/verilog/uart_regs.v
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8213d 11h /uart16550/trunk/rtl/verilog/uart_regs.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8216d 04h /uart16550/trunk/rtl/verilog/uart_regs.v
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8221d 07h /uart16550/trunk/rtl/verilog/uart_regs.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8223d 05h /uart16550/trunk/rtl/verilog/uart_regs.v
44 fixed more typo bugs gorban 8237d 04h /uart16550/trunk/rtl/verilog/uart_regs.v
43 lsr1r error fixed. mohor 8237d 11h /uart16550/trunk/rtl/verilog/uart_regs.v
42 ti_int_pnd error fixed. mohor 8237d 11h /uart16550/trunk/rtl/verilog/uart_regs.v
41 ti_int_d error fixed. mohor 8237d 11h /uart16550/trunk/rtl/verilog/uart_regs.v
40 Synthesis bugs fixed. Some other minor changes gorban 8239d 13h /uart16550/trunk/rtl/verilog/uart_regs.v
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8241d 11h /uart16550/trunk/rtl/verilog/uart_regs.v
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8242d 08h /uart16550/trunk/rtl/verilog/uart_regs.v
36 no message mohor 8247d 16h /uart16550/trunk/rtl/verilog/uart_regs.v
35 Fixes to break and timeout conditions gorban 8249d 11h /uart16550/trunk/rtl/verilog/uart_regs.v
34 fixed parity sending and tx_fifo resets over- and underrun gorban 8251d 09h /uart16550/trunk/rtl/verilog/uart_regs.v
33 Small synopsis fixes gorban 8260d 16h /uart16550/trunk/rtl/verilog/uart_regs.v
32 Changes data_out to be synchronous again as it should have been. gorban 8261d 10h /uart16550/trunk/rtl/verilog/uart_regs.v

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