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[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_rfifo.v] - Rev 88

Rev	Log message	Author	Age	Path
88	added clearing the receiver fifo statuses on resets	gorban	7706d 12h	/uart16550/trunk/rtl/verilog/uart_rfifo.v
87	This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.	gorban	7736d 14h	/uart16550/trunk/rtl/verilog/uart_rfifo.v
84	The uart_defines.v file is included again in sources.	gorban	8053d 09h	/uart16550/trunk/rtl/verilog/uart_rfifo.v
79	Bug Fixes: * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. Problem reported by Kenny.Tung. * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. Improvements: * Made FIFO's as general inferrable memory where possible. So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). This saves about 1/3 of the Slice count and reduces P&R and synthesis times. * Added optional baudrate output (baud_o). This is identical to BAUDOUT* signal on 16550 chip. It outputs 16xbit_clock_rate - the divided clock. It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.	gorban	8060d 08h	/uart16550/trunk/rtl/verilog/uart_rfifo.v