URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [rtl/] [verilog/] [uart_transmitter.v] - Rev 39

Rev	Log message	Author	Age	Path
39	Comments in Slovene language deleted, few small fixes for better work of old tools. IRQs need to be fix.	mohor	8256d 14h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
37	Heavily rewritten interrupt and LSR subsystems. Many bugs hopefully squashed.	gorban	8257d 12h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
34	fixed parity sending and tx_fifo resets over- and underrun	gorban	8266d 12h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
33	Small synopsis fixes	gorban	8275d 19h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
29	Things connected to parity changed. Clock devider changed.	mohor	8332d 08h	/uart16550/trunk/rtl/verilog/uart_transmitter.v
27	Stop bit bug fixed. Parity bug fixed. WISHBONE read cycle bug fixed, OE indicator (Overrun Error) bug fixed. PE indicator (Parity Error) bug fixed. Register read bug fixed.	mohor	8333d 13h	/uart16550/trunk/rtl/verilog/uart_transmitter.v