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[/] [uart2bus/] [trunk/] [verilog/] [rtl/] [uart_rx.v] - Rev 9

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9 Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate. motilito 4751d 09h /uart2bus/trunk/verilog/rtl/uart_rx.v
2 Uploaded the initial project version. motilito 5396d 07h /uart2bus/trunk/verilog/rtl/uart_rx.v

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