URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk] - Rev 9

Rev	Log message	Author	Age	Path
9	Corrected problems in the UART modules that prevented it to operate with 1 stop bit with high data rate.	motilito	4582d 18h	/uart2bus/trunk
8	Updated core description document to include Lattice device synthesis results.	motilito	4803d 23h	/uart2bus/trunk
7	Updated the Scilab script for Scilab 5.3 version. Previous versions might not work.	motilito	4825d 08h	/uart2bus/trunk
6	Commit VHDL description source with basic test benches	smuller	5074d 17h	/uart2bus/trunk
5	Add structure for VHDL (verilog similar tree).	smuller	5086d 10h	/uart2bus/trunk
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5181d 09h	/uart2bus/trunk
3		motilito	5227d 15h	/uart2bus/trunk
2	Uploaded the initial project version.	motilito	5227d 16h	/uart2bus/trunk
1	The project and the structure was created	root	5230d 09h	/uart2bus/trunk