URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [test] - Rev 10

Rev	Log message	Author	Age	Path
10	add maximum simulation time + refine the reporting phase	HanySalah	2571d 09h	/uart2bus_testbench/trunk/tb/test
9	Change the verbosity of passed test message to be UVM_HIGH + add the reporting message in the report phase in testfile	HanySalah	2571d 10h	/uart2bus_testbench/trunk/tb/test
8		HanySalah	2700d 16h	/uart2bus_testbench/trunk/tb/test
3		HanySalah	3059d 21h	/uart2bus_testbench/trunk/tb/test
2	Initial Version	HanySalah	3085d 10h	/uart2bus_testbench/trunk/tb/test