OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block/] [trunk/] [hdl/] [iseProject/] [isim.cmd] - Rev 35

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
35 Bug really fixed... Some testbench results saved... Now would be a nice Idea to start thinking about documentation... leonardoaraujo.santos 4566d 17h /uart_block/trunk/hdl/iseProject/isim.cmd
21 Preparing to rewrite uart_control, adding pin to indicate data available at the RX leonardoaraujo.santos 4570d 07h /uart_block/trunk/hdl/iseProject/isim.cmd
19 Working on the top wishbone slave testbench.... still need some fixes (Both on the testbench and on the uart_control.vhd) leonardoaraujo.santos 4570d 16h /uart_block/trunk/hdl/iseProject/isim.cmd
16 Adding testbench for wishbone slave module leonardoaraujo.santos 4571d 00h /uart_block/trunk/hdl/iseProject/isim.cmd
10 Working on the control unit part leonardoaraujo.santos 4572d 05h /uart_block/trunk/hdl/iseProject/isim.cmd
8 Solving some bugs in baud_generator.vhd leonardoaraujo.santos 4573d 03h /uart_block/trunk/hdl/iseProject/isim.cmd
6 Adding baud generator leonardoaraujo.santos 4574d 00h /uart_block/trunk/hdl/iseProject/isim.cmd
2 Starting here .... leonardoaraujo.santos 4581d 04h /uart_block/trunk/hdl/iseProject/isim.cmd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.