URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

[/] [uart_block] - Rev 18

Rev	Log message	Author	Age	Path
18	sdsd	leonardoaraujo.santos	4546d 00h	/uart_block
17	Working on slave testbench and fixing some bugs	leonardoaraujo.santos	4546d 01h	/uart_block
16	Adding testbench for wishbone slave module	leonardoaraujo.santos	4546d 01h	/uart_block
15	Taking out some warnings and transparent latches from the design	leonardoaraujo.santos	4546d 02h	/uart_block
14	Fixing some warnings... Adding wishbone slave	leonardoaraujo.santos	4546d 22h	/uart_block
13	Working on uart_control testbench... also applying some fixes...	leonardoaraujo.santos	4546d 23h	/uart_block
12	Working on the communication blocks	leonardoaraujo.santos	4547d 00h	/uart_block
11	Adding uart_communication_block	leonardoaraujo.santos	4547d 02h	/uart_block
10	Working on the control unit part	leonardoaraujo.santos	4547d 06h	/uart_block
9	Adding Control unit for uart block	leonardoaraujo.santos	4547d 18h	/uart_block
8	Solving some bugs in baud_generator.vhd	leonardoaraujo.santos	4548d 04h	/uart_block
7	Remember to clean project files	leonardoaraujo.santos	4549d 01h	/uart_block
6	Adding baud generator	leonardoaraujo.santos	4549d 01h	/uart_block
5	Adding sequential division (32 cycles per 32 bit word)	leonardoaraujo.santos	4554d 03h	/uart_block
4	Working on receiver	leonardoaraujo.santos	4556d 03h	/uart_block
3	Deleting unused files and changing tests	leonardoaraujo.santos	4556d 04h	/uart_block
2	Starting here ....	leonardoaraujo.santos	4556d 05h	/uart_block
1	The project and the structure was created	root	4556d 20h	/uart_block