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[/] [usbhostslave/] [trunk/] [RTL/] [hostController/] [sendpacketcheckpreamble.v] - Rev 43

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Rev Log message Author Age Path
43 Fixed bugs related to accessing low speed device via hub sfielding 5003d 12h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
40 New directory structure. root 5581d 02h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 5778d 11h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
34 *** empty log message *** sfielding 6457d 06h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
22 Release 1.2 sfielding 6459d 08h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
14 Added LS keep alive, fixed clock recovery bug sfielding 7043d 07h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
9 Fixed bus turn-around problems, added version number sfielding 7090d 22h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
7 Fixed some blocking assignments, changed module name, fixed SOF_TX_TIME sfielding 7110d 21h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
5 Removed html documentation sfielding 7123d 21h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v
2 Created sfielding 7192d 08h /usbhostslave/trunk/RTL/hostController/sendpacketcheckpreamble.v

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