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[/] [usbhostslave/] [trunk/] [RTL/] [include/] [usbHostSlave_h.v] - Rev 43

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Rev Log message Author Age Path
43 Fixed bugs related to accessing low speed device via hub sfielding 4985d 00h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
40 New directory structure. root 5562d 14h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
37 usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project sfielding 5760d 00h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
36 Revision 1.3 - Fixed input metastability and delay hazard issue sfielding 5915d 12h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
22 Release 1.2 sfielding 6440d 20h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
20 Fixed RX clock recovery bug, and RX time out bug sfielding 6671d 19h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
18 Added dual clock, fixed slave bug, added reset register sfielding 6776d 09h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
16 Added bus access to SOF timer sfielding 6915d 12h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
14 Added LS keep alive, fixed clock recovery bug sfielding 7024d 20h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
12 try again sfielding 7055d 11h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v
10 Added version number sfielding 7071d 19h /usbhostslave/trunk/RTL/include/usbHostSlave_h.v

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