URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

[/] [usbhostslave/] [trunk/] [RTL/] [wrapper/] [usbHostSlave.v] - Rev 43

Rev	Log message	Author	Age	Path
43	Fixed bugs related to accessing low speed device via hub	sfielding	4992d 09h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
40	New directory structure.	root	5569d 23h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
37	usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project	sfielding	5767d 09h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
22	Release 1.2	sfielding	6448d 05h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
20	Fixed RX clock recovery bug, and RX time out bug	sfielding	6679d 03h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
18	Added dual clock, fixed slave bug, added reset register	sfielding	6783d 18h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
9	Fixed bus turn-around problems, added version number	sfielding	7079d 19h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
5	Removed html documentation	sfielding	7112d 19h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v
2	Created	sfielding	7181d 05h	/usbhostslave/trunk/RTL/wrapper/usbHostSlave.v