URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk/] [rtl/] [verilog] - Rev 18

Rev	Log message	Author	Age	Path
18	ADDR and DATA width set to 8 resp 32	unneback	5270d 06h	/versatile_fifo/trunk/rtl/verilog
17	based on updated versatile counter	unneback	5274d 05h	/versatile_fifo/trunk/rtl/verilog
16	changed power of two style	unneback	5537d 14h	/versatile_fifo/trunk/rtl/verilog
15	doc updated gray_counter_defines added dual port RAM updated	unneback	5541d 08h	/versatile_fifo/trunk/rtl/verilog
13	adr update	unneback	5586d 17h	/versatile_fifo/trunk/rtl/verilog
12	no mux on dual port mem read	unneback	5599d 10h	/versatile_fifo/trunk/rtl/verilog
11	name conflict wptr1 changed to wptr1_cnt etc	unneback	5599d 13h	/versatile_fifo/trunk/rtl/verilog
10	rptr2	unneback	5599d 14h	/versatile_fifo/trunk/rtl/verilog
9		unneback	5605d 09h	/versatile_fifo/trunk/rtl/verilog
8		unneback	5605d 10h	/versatile_fifo/trunk/rtl/verilog
7		unneback	5605d 10h	/versatile_fifo/trunk/rtl/verilog
6		unneback	5605d 13h	/versatile_fifo/trunk/rtl/verilog
5	async compare for fifo full and empty	unneback	5605d 13h	/versatile_fifo/trunk/rtl/verilog
4		unneback	5605d 17h	/versatile_fifo/trunk/rtl/verilog
2		unneback	5605d 18h	/versatile_fifo/trunk/rtl/verilog