OpenCores
URL https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk

Subversion Repositories versatile_fifo

[/] [versatile_fifo/] [trunk] - Rev 32

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
32 fixed SYN directives marcus.erlandsson 5128d 11h /versatile_fifo/trunk
31 port map unneback 5199d 04h /versatile_fifo/trunk
30 port map unneback 5199d 05h /versatile_fifo/trunk
29 ACTEL syn define unneback 5207d 02h /versatile_fifo/trunk
28 ACTEL async dual way FIFO unneback 5214d 12h /versatile_fifo/trunk
27 initial commit, dual way simplex FIFO unneback 5215d 03h /versatile_fifo/trunk
26 added ACTEL synthesis directive as define, +ACTEL unneback 5215d 03h /versatile_fifo/trunk
25 DFF SR as separate logic unneback 5354d 23h /versatile_fifo/trunk
24 updated fifo interfaces with re/rd and we/wr unneback 5355d 13h /versatile_fifo/trunk
23 unneback 5358d 02h /versatile_fifo/trunk
22 async fifo with multiple queues unneback 5358d 02h /versatile_fifo/trunk
21 added DFF SR unneback 5372d 00h /versatile_fifo/trunk
20 unneback 5372d 07h /versatile_fifo/trunk
19 DFF with async clear and set for Altera cycloneIV unneback 5373d 13h /versatile_fifo/trunk
18 ADDR and DATA width set to 8 resp 32 unneback 5374d 03h /versatile_fifo/trunk
17 based on updated versatile counter unneback 5378d 01h /versatile_fifo/trunk
16 changed power of two style unneback 5641d 11h /versatile_fifo/trunk
15 doc updated
gray_counter_defines added
dual port RAM updated
unneback 5645d 05h /versatile_fifo/trunk
14 added PDF unneback 5689d 11h /versatile_fifo/trunk
13 adr update unneback 5690d 13h /versatile_fifo/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.