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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 38

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Rev Log message Author Age Path
38 updated andor mux unneback 4869d 01h /versatile_library/trunk/rtl/verilog
37 corrected polynom with length 20 unneback 4874d 21h /versatile_library/trunk/rtl/verilog
36 added generic andor_mux unneback 4876d 06h /versatile_library/trunk/rtl/verilog
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4876d 17h /versatile_library/trunk/rtl/verilog
34 added vl_mux2_andor and vl_mux3_andor unneback 4876d 17h /versatile_library/trunk/rtl/verilog
33 updated wb3wb3_bridge unneback 4889d 19h /versatile_library/trunk/rtl/verilog
32 added vl_pll for ALTERA (cycloneIII) unneback 4897d 05h /versatile_library/trunk/rtl/verilog
31 sync FIFO updated unneback 4917d 00h /versatile_library/trunk/rtl/verilog
30 updated counter for level1 and level2 function unneback 4917d 01h /versatile_library/trunk/rtl/verilog
29 updated counter for level1 and level2 function unneback 4917d 01h /versatile_library/trunk/rtl/verilog
28 added sync simplex FIFO unneback 4918d 02h /versatile_library/trunk/rtl/verilog
27 added sync simplex FIFO unneback 4918d 02h /versatile_library/trunk/rtl/verilog
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4918d 03h /versatile_library/trunk/rtl/verilog
25 added sync FIFO unneback 4918d 17h /versatile_library/trunk/rtl/verilog
24 added vl_dff_ce_set unneback 4920d 00h /versatile_library/trunk/rtl/verilog
23 fixed port map error in async fifo 1r1w unneback 4920d 15h /versatile_library/trunk/rtl/verilog
22 added binary counters unneback 4920d 20h /versatile_library/trunk/rtl/verilog
21 reg -> wire in and or mux in logic unneback 4921d 16h /versatile_library/trunk/rtl/verilog
18 naming convention vl_ unneback 4923d 03h /versatile_library/trunk/rtl/verilog
17 unneback 4986d 17h /versatile_library/trunk/rtl/verilog

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