OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 44

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
44 added target independet IO functionns unneback 4871d 02h /versatile_library/trunk/rtl/verilog
43 added logic for parity generation and check unneback 4875d 06h /versatile_library/trunk/rtl/verilog
42 updated mux_andor unneback 4879d 06h /versatile_library/trunk/rtl/verilog
41 typo in registers.v unneback 4879d 07h /versatile_library/trunk/rtl/verilog
40 new build environment with custom.v added as a result file unneback 4879d 07h /versatile_library/trunk/rtl/verilog
39 added simple port prio based wb arbiter unneback 4880d 04h /versatile_library/trunk/rtl/verilog
38 updated andor mux unneback 4880d 04h /versatile_library/trunk/rtl/verilog
37 corrected polynom with length 20 unneback 4886d 01h /versatile_library/trunk/rtl/verilog
36 added generic andor_mux unneback 4887d 09h /versatile_library/trunk/rtl/verilog
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4887d 20h /versatile_library/trunk/rtl/verilog
34 added vl_mux2_andor and vl_mux3_andor unneback 4887d 20h /versatile_library/trunk/rtl/verilog
33 updated wb3wb3_bridge unneback 4900d 23h /versatile_library/trunk/rtl/verilog
32 added vl_pll for ALTERA (cycloneIII) unneback 4908d 08h /versatile_library/trunk/rtl/verilog
31 sync FIFO updated unneback 4928d 04h /versatile_library/trunk/rtl/verilog
30 updated counter for level1 and level2 function unneback 4928d 04h /versatile_library/trunk/rtl/verilog
29 updated counter for level1 and level2 function unneback 4928d 04h /versatile_library/trunk/rtl/verilog
28 added sync simplex FIFO unneback 4929d 06h /versatile_library/trunk/rtl/verilog
27 added sync simplex FIFO unneback 4929d 06h /versatile_library/trunk/rtl/verilog
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4929d 07h /versatile_library/trunk/rtl/verilog
25 added sync FIFO unneback 4929d 20h /versatile_library/trunk/rtl/verilog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.