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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 139

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Rev Log message Author Age Path
139 unneback 4956d 20h /versatile_library/trunk/rtl/verilog/Makefile
75 added wb to avalon bridge unneback 5051d 06h /versatile_library/trunk/rtl/verilog/Makefile
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 5099d 23h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 5239d 23h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 5248d 03h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 5269d 19h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 5297d 00h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5298d 03h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 5298d 16h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 5300d 20h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 5303d 03h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 5374d 03h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 5389d 19h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 5393d 22h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 5396d 17h /versatile_library/trunk/rtl/verilog/Makefile

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