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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 39

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Rev Log message Author Age Path
33 updated wb3wb3_bridge unneback 4889d 19h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 4917d 01h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4918d 03h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 4918d 17h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 4920d 20h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 4923d 04h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 4994d 03h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 5009d 19h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 5013d 23h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 5016d 18h /versatile_library/trunk/rtl/verilog/Makefile

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