URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 36

Rev	Log message	Author	Age	Path
31	sync FIFO updated	unneback	4922d 11h	/versatile_library/trunk/rtl/verilog/memories.v
28	added sync simplex FIFO	unneback	4923d 12h	/versatile_library/trunk/rtl/verilog/memories.v
27	added sync simplex FIFO	unneback	4923d 12h	/versatile_library/trunk/rtl/verilog/memories.v
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4923d 14h	/versatile_library/trunk/rtl/verilog/memories.v
25	added sync FIFO	unneback	4924d 03h	/versatile_library/trunk/rtl/verilog/memories.v
23	fixed port map error in async fifo 1r1w	unneback	4926d 02h	/versatile_library/trunk/rtl/verilog/memories.v
21	reg -> wire in and or mux in logic	unneback	4927d 03h	/versatile_library/trunk/rtl/verilog/memories.v
18	naming convention vl_	unneback	4928d 14h	/versatile_library/trunk/rtl/verilog/memories.v
14	reg -> wire for various signals	unneback	4998d 16h	/versatile_library/trunk/rtl/verilog/memories.v
11	async fifo simplex	unneback	5000d 05h	/versatile_library/trunk/rtl/verilog/memories.v
7	mem update	unneback	5002d 05h	/versatile_library/trunk/rtl/verilog/memories.v
5	memories added	unneback	5015d 05h	/versatile_library/trunk/rtl/verilog/memories.v