URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 84

Rev	Log message	Author	Age	Path
75	added wb to avalon bridge	unneback	4686d 14h	/versatile_library/trunk/rtl/verilog/registers.v
64	SPR reset value	unneback	4733d 12h	/versatile_library/trunk/rtl/verilog/registers.v
60	added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed	unneback	4735d 08h	/versatile_library/trunk/rtl/verilog/registers.v
48	wb updated	unneback	4774d 09h	/versatile_library/trunk/rtl/verilog/registers.v
41	typo in registers.v	unneback	4883d 12h	/versatile_library/trunk/rtl/verilog/registers.v
40	new build environment with custom.v added as a result file	unneback	4883d 12h	/versatile_library/trunk/rtl/verilog/registers.v
29	updated counter for level1 and level2 function	unneback	4932d 09h	/versatile_library/trunk/rtl/verilog/registers.v
24	added vl_dff_ce_set	unneback	4935d 09h	/versatile_library/trunk/rtl/verilog/registers.v
18	naming convention vl_	unneback	4938d 12h	/versatile_library/trunk/rtl/verilog/registers.v
17		unneback	5002d 01h	/versatile_library/trunk/rtl/verilog/registers.v
15	added delay line	unneback	5008d 09h	/versatile_library/trunk/rtl/verilog/registers.v
10	added dff_ce_clear	unneback	5012d 01h	/versatile_library/trunk/rtl/verilog/registers.v
8	added dff_ce_clear	unneback	5012d 01h	/versatile_library/trunk/rtl/verilog/registers.v
5	memories added	unneback	5025d 03h	/versatile_library/trunk/rtl/verilog/registers.v
3	various updates counter added	unneback	5032d 02h	/versatile_library/trunk/rtl/verilog/registers.v