OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Rev 60

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4733d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
59 added WB RAM B3 with byte enable unneback 4734d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
56 WB B4 RAM we fix unneback 4763d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
55 added WB_B4RAM with byte enable unneback 4765d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
54 added WB_B4RAM with byte enable unneback 4765d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
53 added WB_B4RAM with byte enable unneback 4765d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
52 added WB_B4RAM with byte enable unneback 4765d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
51 added WB_B4RAM with byte enable unneback 4765d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
50 added WB_B4RAM with byte enable unneback 4765d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
49 added WB_B4RAM with byte enable unneback 4765d 21h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
48 wb updated unneback 4772d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
46 updated parity unneback 4868d 20h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
45 updated timing in io models unneback 4870d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
44 added target independet IO functionns unneback 4873d 14h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
43 added logic for parity generation and check unneback 4877d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
42 updated mux_andor unneback 4881d 17h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
40 new build environment with custom.v added as a result file unneback 4881d 18h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
39 added simple port prio based wb arbiter unneback 4882d 15h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
38 updated andor mux unneback 4882d 16h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v
37 corrected polynom with length 20 unneback 4888d 12h /versatile_library/trunk/rtl/verilog/versatile_library_actel.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.