URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl] - Rev 33

Rev	Log message	Author	Age	Path
33	updated wb3wb3_bridge	unneback	4904d 06h	/versatile_library/trunk/rtl
32	added vl_pll for ALTERA (cycloneIII)	unneback	4911d 16h	/versatile_library/trunk/rtl
31	sync FIFO updated	unneback	4931d 11h	/versatile_library/trunk/rtl
30	updated counter for level1 and level2 function	unneback	4931d 12h	/versatile_library/trunk/rtl
29	updated counter for level1 and level2 function	unneback	4931d 12h	/versatile_library/trunk/rtl
28	added sync simplex FIFO	unneback	4932d 13h	/versatile_library/trunk/rtl
27	added sync simplex FIFO	unneback	4932d 13h	/versatile_library/trunk/rtl
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4932d 14h	/versatile_library/trunk/rtl
25	added sync FIFO	unneback	4933d 04h	/versatile_library/trunk/rtl
24	added vl_dff_ce_set	unneback	4934d 11h	/versatile_library/trunk/rtl
23	fixed port map error in async fifo 1r1w	unneback	4935d 02h	/versatile_library/trunk/rtl
22	added binary counters	unneback	4935d 07h	/versatile_library/trunk/rtl
21	reg -> wire in and or mux in logic	unneback	4936d 03h	/versatile_library/trunk/rtl
18	naming convention vl_	unneback	4937d 15h	/versatile_library/trunk/rtl
17		unneback	5001d 04h	/versatile_library/trunk/rtl
15	added delay line	unneback	5007d 12h	/versatile_library/trunk/rtl
14	reg -> wire for various signals	unneback	5007d 17h	/versatile_library/trunk/rtl
13	cosmetic update	unneback	5007d 18h	/versatile_library/trunk/rtl
12	added wishbone comliant modules	unneback	5008d 14h	/versatile_library/trunk/rtl
11	async fifo simplex	unneback	5009d 05h	/versatile_library/trunk/rtl