URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl] - Rev 34

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Rev	Log message	Author	Age	Path
34	added vl_mux2_andor and vl_mux3_andor	unneback	4882d 19h	/versatile_library/trunk/rtl
33	updated wb3wb3_bridge	unneback	4895d 21h	/versatile_library/trunk/rtl
32	added vl_pll for ALTERA (cycloneIII)	unneback	4903d 07h	/versatile_library/trunk/rtl
31	sync FIFO updated	unneback	4923d 02h	/versatile_library/trunk/rtl
30	updated counter for level1 and level2 function	unneback	4923d 02h	/versatile_library/trunk/rtl
29	updated counter for level1 and level2 function	unneback	4923d 02h	/versatile_library/trunk/rtl
28	added sync simplex FIFO	unneback	4924d 04h	/versatile_library/trunk/rtl
27	added sync simplex FIFO	unneback	4924d 04h	/versatile_library/trunk/rtl
26	typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q	unneback	4924d 05h	/versatile_library/trunk/rtl
25	added sync FIFO	unneback	4924d 19h	/versatile_library/trunk/rtl
24	added vl_dff_ce_set	unneback	4926d 02h	/versatile_library/trunk/rtl
23	fixed port map error in async fifo 1r1w	unneback	4926d 17h	/versatile_library/trunk/rtl
22	added binary counters	unneback	4926d 22h	/versatile_library/trunk/rtl
21	reg -> wire in and or mux in logic	unneback	4927d 18h	/versatile_library/trunk/rtl
18	naming convention vl_	unneback	4929d 05h	/versatile_library/trunk/rtl
17		unneback	4992d 19h	/versatile_library/trunk/rtl
15	added delay line	unneback	4999d 03h	/versatile_library/trunk/rtl
14	reg -> wire for various signals	unneback	4999d 08h	/versatile_library/trunk/rtl
13	cosmetic update	unneback	4999d 09h	/versatile_library/trunk/rtl
12	added wishbone comliant modules	unneback	5000d 05h	/versatile_library/trunk/rtl

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Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl] - Rev 34

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