URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [bench/] [wb0_ddr.fzm] - Rev 89

Rev	Log message	Author	Age	Path
89		unneback	5122d 09h	/versatile_mem_ctrl/tags/Rev1/bench/wb0_ddr.fzm
75		mikaeljf	5234d 10h	/versatile_mem_ctrl/trunk/bench/wb0_ddr.fzm
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5305d 09h	/versatile_mem_ctrl/trunk/bench/wb0_ddr.fzm
12	Minor update of whishbone FSMs in TB	mikaeljf	5405d 15h	/versatile_mem_ctrl/trunk/bench/wb0_ddr.fzm
11	Initial version with support for DDR	mikaeljf	5406d 03h	/versatile_mem_ctrl/trunk/bench/wb0_ddr.fzm