URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [bench] - Rev 89

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Rev	Log message	Author	Age	Path
89		unneback	5057d 04h	/versatile_mem_ctrl/tags/Rev1/bench
82		mikaeljf	5115d 10h	/versatile_mem_ctrl/trunk/bench
80		mikaeljf	5116d 08h	/versatile_mem_ctrl/trunk/bench
75		mikaeljf	5169d 05h	/versatile_mem_ctrl/trunk/bench
74	Minor update of rtl Makefile.	mikaeljf	5173d 04h	/versatile_mem_ctrl/trunk/bench
70		mikaeljf	5176d 12h	/versatile_mem_ctrl/trunk/bench
69		mikaeljf	5177d 09h	/versatile_mem_ctrl/trunk/bench
35	work for limited test case	unneback	5198d 04h	/versatile_mem_ctrl/trunk/bench
33	work for limited test case, no cke inhibit for fifo empty	unneback	5198d 07h	/versatile_mem_ctrl/trunk/bench
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5201d 11h	/versatile_mem_ctrl/trunk/bench
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5207d 04h	/versatile_mem_ctrl/trunk/bench
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5207d 06h	/versatile_mem_ctrl/trunk/bench
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5236d 05h	/versatile_mem_ctrl/trunk/bench
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5239d 04h	/versatile_mem_ctrl/trunk/bench
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5240d 05h	/versatile_mem_ctrl/trunk/bench
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5330d 07h	/versatile_mem_ctrl/trunk/bench
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5330d 10h	/versatile_mem_ctrl/trunk/bench
12	Minor update of whishbone FSMs in TB	mikaeljf	5340d 11h	/versatile_mem_ctrl/trunk/bench
11	Initial version with support for DDR	mikaeljf	5340d 22h	/versatile_mem_ctrl/trunk/bench
10		unneback	5368d 06h	/versatile_mem_ctrl/trunk/bench

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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [bench] - Rev 89

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