URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [tags/] [Rev1/] [syn] - Rev 93

Rev	Log message	Author	Age	Path
93		unneback	5064d 03h	/versatile_mem_ctrl/tags/Rev1/syn
86		mikaeljf	5116d 11h	/versatile_mem_ctrl/trunk/syn
84		mikaeljf	5121d 10h	/versatile_mem_ctrl/trunk/syn
83		mikaeljf	5122d 05h	/versatile_mem_ctrl/trunk/syn
81		mikaeljf	5123d 06h	/versatile_mem_ctrl/trunk/syn
75		mikaeljf	5176d 04h	/versatile_mem_ctrl/trunk/syn
30	Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts.	mikaeljf	5210d 03h	/versatile_mem_ctrl/trunk/syn
22	Updated the Altera timing constraints file, also minor updates of defines file and Makefile.	mikaeljf	5229d 22h	/versatile_mem_ctrl/trunk/syn
21	Updated the Altera timing constraints file (.sdc).	mikaeljf	5234d 01h	/versatile_mem_ctrl/trunk/syn
20	Minor update of sdc-file.	mikaeljf	5236d 03h	/versatile_mem_ctrl/trunk/syn
19	Added do-file for Modelsim waveform viewer.	mikaeljf	5242d 07h	/versatile_mem_ctrl/trunk/syn
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5247d 04h	/versatile_mem_ctrl/trunk/syn
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5337d 09h	/versatile_mem_ctrl/trunk/syn