URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench/] [tb.v] - Rev 80

Rev	Log message	Author	Age	Path
80		mikaeljf	5277d 12h	/versatile_mem_ctrl/trunk/bench/tb.v
35	work for limited test case	unneback	5359d 08h	/versatile_mem_ctrl/trunk/bench/tb.v
33	work for limited test case, no cke inhibit for fifo empty	unneback	5359d 11h	/versatile_mem_ctrl/trunk/bench/tb.v
32	Updated the testbench to match the new wishbone interface.	mikaeljf	5362d 15h	/versatile_mem_ctrl/trunk/bench/tb.v
29	Adapted the test bench to the new wishbone interface.	mikaeljf	5368d 08h	/versatile_mem_ctrl/trunk/bench/tb.v
28	Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'.	mikaeljf	5368d 10h	/versatile_mem_ctrl/trunk/bench/tb.v
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5401d 08h	/versatile_mem_ctrl/trunk/bench/tb.v
14	Added external feedback of DDR SDRAM clock.	mikaeljf	5491d 11h	/versatile_mem_ctrl/trunk/bench/tb.v
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5491d 14h	/versatile_mem_ctrl/trunk/bench/tb.v
11	Initial version with support for DDR	mikaeljf	5502d 02h	/versatile_mem_ctrl/trunk/bench/tb.v
9	testbench	unneback	5529d 10h	/versatile_mem_ctrl/trunk/bench/tb.v