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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [bench] - Rev 106

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106 added texinfo User guide and updated fsm unneback 5012d 20h /versatile_mem_ctrl/trunk/bench
99 updated stimuli with automatic check unneback 5051d 03h /versatile_mem_ctrl/trunk/bench
94 new TB unneback 5198d 06h /versatile_mem_ctrl/trunk/bench
82 mikaeljf 5267d 09h /versatile_mem_ctrl/trunk/bench
80 mikaeljf 5268d 07h /versatile_mem_ctrl/trunk/bench
75 mikaeljf 5321d 04h /versatile_mem_ctrl/trunk/bench
74 Minor update of rtl Makefile. mikaeljf 5325d 03h /versatile_mem_ctrl/trunk/bench
70 mikaeljf 5328d 11h /versatile_mem_ctrl/trunk/bench
69 mikaeljf 5329d 08h /versatile_mem_ctrl/trunk/bench
35 work for limited test case unneback 5350d 03h /versatile_mem_ctrl/trunk/bench
33 work for limited test case, no cke inhibit for fifo empty unneback 5350d 06h /versatile_mem_ctrl/trunk/bench
32 Updated the testbench to match the new wishbone interface. mikaeljf 5353d 10h /versatile_mem_ctrl/trunk/bench
29 Adapted the test bench to the new wishbone interface. mikaeljf 5359d 03h /versatile_mem_ctrl/trunk/bench
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5359d 05h /versatile_mem_ctrl/trunk/bench
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5388d 04h /versatile_mem_ctrl/trunk/bench
17 Modified rtl Makefile and tb_defines.v mikaeljf 5391d 03h /versatile_mem_ctrl/trunk/bench
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5392d 04h /versatile_mem_ctrl/trunk/bench
14 Added external feedback of DDR SDRAM clock. mikaeljf 5482d 06h /versatile_mem_ctrl/trunk/bench
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5482d 09h /versatile_mem_ctrl/trunk/bench
12 Minor update of whishbone FSMs in TB mikaeljf 5492d 09h /versatile_mem_ctrl/trunk/bench

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