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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] - Rev 101

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Rev Log message Author Age Path
101 cleaning up unneback 4957d 05h /versatile_mem_ctrl/trunk/rtl/verilog
100 unneback 4957d 05h /versatile_mem_ctrl/trunk/rtl/verilog
98 updates unneback 5060d 10h /versatile_mem_ctrl/trunk/rtl/verilog
97 updated tb and sdram16 unneback 5060d 23h /versatile_mem_ctrl/trunk/rtl/verilog
95 new files unneback 5096d 00h /versatile_mem_ctrl/trunk/rtl/verilog
86 mikaeljf 5167d 12h /versatile_mem_ctrl/trunk/rtl/verilog
85 Added a versatile_mem_ctrl specific version of the flag generation module in the versatile fifo. mikaeljf 5168d 12h /versatile_mem_ctrl/trunk/rtl/verilog
84 mikaeljf 5172d 11h /versatile_mem_ctrl/trunk/rtl/verilog
82 mikaeljf 5173d 11h /versatile_mem_ctrl/trunk/rtl/verilog
81 mikaeljf 5174d 07h /versatile_mem_ctrl/trunk/rtl/verilog
80 mikaeljf 5174d 09h /versatile_mem_ctrl/trunk/rtl/verilog
79 Added defines that fix bugs with slow wishbone clocks doing burst writes julius 5211d 22h /versatile_mem_ctrl/trunk/rtl/verilog
78 Burst writing working again, although its mostly hardcoded to burst 4. Also added a fix for when the RAM and bus clocks are about the same speed, to avoid buffer overrun julius 5214d 05h /versatile_mem_ctrl/trunk/rtl/verilog
77 SDR 16 registering of current_fifo_empty signal in top, appropriate control alterations in fsm_sdr_16 julius 5222d 04h /versatile_mem_ctrl/trunk/rtl/verilog
76 Changed SDR16 synthesis useioff location, fsm_wb acking logic, default SDR build is for 16m part now julius 5227d 05h /versatile_mem_ctrl/trunk/rtl/verilog
75 mikaeljf 5227d 06h /versatile_mem_ctrl/trunk/rtl/verilog
74 Minor update of rtl Makefile. mikaeljf 5231d 05h /versatile_mem_ctrl/trunk/rtl/verilog
73 Minor updates to fix lost revisions 69 and 70. mikaeljf 5231d 06h /versatile_mem_ctrl/trunk/rtl/verilog
72 Restored lost revisions 69 and 70. mikaeljf 5231d 06h /versatile_mem_ctrl/trunk/rtl/verilog
71 Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes julius 5231d 07h /versatile_mem_ctrl/trunk/rtl/verilog

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