URL https://opencores.org/ocsvn/versatile_mem_ctrl/versatile_mem_ctrl/trunk

Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 18

Rev	Log message	Author	Age	Path
18	Updated the rtl/verilog Makefile and the bench Makefile.	mikaeljf	5294d 19h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
17	Modified rtl Makefile and tb_defines.v	mikaeljf	5297d 18h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
15	Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.	mikaeljf	5298d 18h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
13	Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback.	mikaeljf	5388d 23h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
11	Initial version with support for DDR	mikaeljf	5399d 12h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
6		unneback	5522d 16h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
5	pass initial testing	unneback	5522d 17h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
4		unneback	5523d 20h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
3		unneback	5523d 22h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile
2	initial	unneback	5529d 20h	/versatile_mem_ctrl/trunk/rtl/verilog/Makefile