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[/] [versatile_mem_ctrl/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 42

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42 added pipeline stage for egress FIFO readot unneback 5189d 15h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
39 updated FIFO and SDR 16 unneback 5190d 17h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
37 unneback 5193d 15h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
35 work for limited test case unneback 5193d 23h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
33 work for limited test case, no cke inhibit for fifo empty unneback 5194d 01h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5198d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5203d 00h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
25 unneback 5208d 18h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5209d 05h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5218d 17h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5232d 00h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
17 Modified rtl Makefile and tb_defines.v mikaeljf 5234d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5235d 23h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5326d 04h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
11 Initial version with support for DDR mikaeljf 5336d 17h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
6 unneback 5459d 21h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
5 pass initial testing unneback 5459d 22h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
4 unneback 5461d 01h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
3 unneback 5461d 03h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile
2 initial unneback 5467d 01h /versatile_mem_ctrl/trunk/rtl/verilog/Makefile

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