Rev |
Log message |
Author |
Age |
Path |
71 |
Replacing versatile_mem_ctrl_top with revisino 68 version but with top level ack fix. May lose some of revision 69 and 70 changes |
julius |
5286d 22h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
69 |
|
mikaeljf |
5291d 01h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
64 |
Changed sdr 16 FSM to use defines instead of parameters which were somehow screwing up synplify, reinstated used of sdr_16_defines.v file |
julius |
5293d 15h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
60 |
Added synthesis directives ensuring registering of right signals in IOBs for sdr16 controller. Removed comment stripping from vppreproc command for sdr_16 creation. |
julius |
5297d 23h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
50 |
Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily |
julius |
5304d 17h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
49 |
Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project |
julius |
5304d 19h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
42 |
added pipeline stage for egress FIFO readot |
unneback |
5307d 12h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
39 |
updated FIFO and SDR 16 |
unneback |
5308d 14h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
37 |
|
unneback |
5311d 12h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
35 |
work for limited test case |
unneback |
5311d 20h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
33 |
work for limited test case, no cke inhibit for fifo empty |
unneback |
5311d 22h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
31 |
Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. |
mikaeljf |
5316d 19h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
28 |
Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. |
mikaeljf |
5320d 21h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
25 |
|
unneback |
5326d 14h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
24 |
Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. |
mikaeljf |
5327d 02h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
22 |
Updated the Altera timing constraints file, also minor updates of defines file and Makefile. |
mikaeljf |
5336d 14h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
18 |
Updated the rtl/verilog Makefile and the bench Makefile. |
mikaeljf |
5349d 21h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
17 |
Modified rtl Makefile and tb_defines.v |
mikaeljf |
5352d 19h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
15 |
Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. |
mikaeljf |
5353d 20h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |
13 |
Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. |
mikaeljf |
5444d 01h |
/versatile_mem_ctrl/trunk/rtl/verilog/Makefile |